 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS FEATURES * * * * * * * * Differential PECL (PLL130-68) or LVDS (PLL130-69) output. Accepts any single-ended REFIN input (with as low as 100mV swing). Internal AC coupling of REFIN Input range from 1.0MHz to 1.0 GHz. No Vref required. No external current source required. 2.5 to 3.3V operation. Available in 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) Q_bar VDD 13 NC REFIN NC NC 1 2 3 4 16 15 NC 14 Q 12 11 10 9 NC Q Q_bar OESEL PLL130-6x 5 6 7 8 GND NC DESCRIPTION The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential outputs (PECL for PLL130-68 or LVDS for PLL13069). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDS or PECL. OUTPUT ENABLE LOGICAL LEVELS PLL130-68 OESEL 0 (Default) 1 OECTRL 0 (Default) 1 0 1 (Default) OUTPUT STATE Output enabled Tri-state Tri-state Output enabled OECTRL input: Logical states defined by PECL levels. PLL130-69 OESEL 0 (Default) 1 OECTRL 0 1 (Default) 0 (Default) 1 OUTPUT STATE Tri-state Output enabled Output enabled Tri-state OECTRL input: Logical states defined by CMOS levels. BLOCK DIAGRAM OECTRL REFIN AC Coupling Input Q_BAR Q Amplifier 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1 NC PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS PIN DESCRIPTION Name NC REFIN OECTRL GND OESEL Q_BAR Q VDD Q Q_BAR Pin number 1, 3, 4, 6, 8, 12, 14 2 5 7 9 10 11 13 15 16 Type I I P I O O P O O No connection. Description Reference input signal. The frequency of this signal will be reproduced at the output (after translation to PECL or LVDS level). Output enable input (See OE Logic Table on page 1). Ground connector. Output enable logic selector (See OE Logic Table on page 1). Complementary output. PECL_bar on PLL130-68, LVDS_bar on PLL130-69. True output. PECL on PLL130-68, LVDS on PLL130-69. 3.3V Power supply. Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This output is the same as pin 11. Additional complementary output. PECL_bar on PLL130-68, LVDS_bar on PLL130-69. This output is the same as pin 10. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. General Electrical Specifications PARAMETERS Supply Current (both outputs loaded) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL IDD VDD CONDITIONS Fout = 156.25MHz, PECL Fout = 156.25MHz, LVDS @ Vdd - 1.3V (PECL) @ 1.25V (LVDS) MIN. 45 22 2.97 TYP. 48 25 Same as input Same as input 50 MAX. 51 28 3.63 UNITS mA V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 2 PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS 3. AC Specifications PARAMETERS Input Frequency Input signal swing Output Frequency CONDITIONS REFIN input MIN. 0 100 0 TYP. MAX. 1000 1000 UNITS MHz mV MHz 4. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL VOH VOL CONDITIONS RL = 50 to (VDD - 2V) (see figure) MIN. VDD - 1.025 VDD - 1.810 MAX. VDD - 0.880 VDD - 1.620 UNITS V V 5. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL tr tf CONDITIONS @20/80% - PECL @80/20% - PECL MIN. TYP. 0.2 0.2 MAX. 0.5 0.5 UNITS ns ns PECL Levels Test Circuit OUT VDD OUT PECL Output Skew 50 2.0V 50% 50 OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 3 PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS 6. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL VOD VOD VOH VOL VOS VOS IOXD IOSD CONDITIONS MIN. 247 -50 0.9 1.125 0 TYP. 355 1.4 1.1 1.2 3 1 -5.7 MAX. 454 50 1.6 1.375 25 10 -8 UNITS mV mV V V V mV uA mA (see figure) Vout = VDD or GND RL = 100 V DD = 0V 7. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS C L = 10 pF (see figure) RL = 100 MIN. 0.2 0.2 TYP. 0.5 0.5 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50 CL = 10pF VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 4 PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS PACKAGE INFORMATION Important note: pin 1 indicator (bottom side) is metallized and connected to GND through the leadframe. Traces in contact with the pin 1 indicator may result is short circuit to GND. ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL130-6X PART NUMBER QC TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE Q=QFN Order Number PLL130-68QC-R PLL130-68QC PLL130-69QC-R PLL130-69QC Marking P130-68 P130-68 P130-69 P130-69 Package Option QFN QFN QFN QFN Tape and Reel Tube Tape and Reel Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 5 |
Price & Availability of PLL130-69QI
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |